学帮网求大神人工翻译In summary, the control logic for VBMAR is simple. It can realize high performance at a low cost. We can demonstrate its peak performance using A. A. Chien's model [2], which computes delay of every logic module of a wormhole rou
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求大神人工翻译
In summary, the control logic for VBMAR is simple. It can realize high performance at a low cost. We can demonstrate its peak performance using A. A. Chien's model [2], which computes delay of every logic module of a wormhole router. It is assumed that the 0.8Pm CMOS is used. Based on the model, delays of input, routing, and output control logic of VBMAR router are 3.68, 7.2, and 5.14 nanoseconds respectively. Clock cycle of the router should be larger than the delay of its slowest stage. So we set the clock cycle T = 10ns > MAX(3.68, 7.2, 5.14 ) = 7.2 ns. Thus the clock frequency is 100MHz. Because a physical channel includes 18 data wires, the bandwidth of a single channel is more than 200MB/s or 3.2Gb/s.
总之,这一针对VBMAR的控制逻辑是简单的,它可以实现高性能低成本.它可以用A.A Chien的模型类展示他的最佳性能,它（指A.A Chien的模型）计算虫孔路由器的每一个逻辑模块的延迟,它假设0.8Pm的CMOS被使用.根据这一模型,VBMAR输入,路由和输出逻辑的延迟分别是3.68、7.2和5.14纳秒.路由器的时钟周期应该大于它的最慢的一级的延迟,所以我们设定时钟周期T=10ns>最大值（MAX）（3.68、7.2、5.14）=7.2ns.这样时钟频率是100兆赫.因为一个物理通道包括有18条数据线,所以单一通道的带宽大于200MB/s或3.2GB/s.